Self-timed pipeline with adder
- Resource Type
- Conference
- Authors
- Compton, J.; Albicki, A.
- Source
- [1992] Proceedings of the Second Great Lakes Symposium on VLSI VLSI, 1992., Proceedings of the Second Great Lakes Symposium on. :109-113 1992
- Subject
- Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Computing and Processing
Signal Processing and Analysis
Pipelines
Adders
Latches
Detectors
Timing
Combinational circuits
Rails
Monitoring
Logic design
Wires
- Language
This paper describes the design of an asynchronous pipeline structure comprising a ripple carry adder and registers placed before and after the adder. A scheme was created for monitoring the ripple of the cab through the adder. This scheme provides a means of determining when the addition is complete. The design approach uses transmission gate logic throughout. Results of SPICE simulation on the various building blocks of the circuit are presented.ETX