Embedded JPEG encoder IP core and memory efficient preprocessing architecture for scanner
- Resource Type
- Conference
- Authors
- Chung-Jr Lian; Liang-Gee Chen; Hao-Chieh Chang; Yung-Chi Chang
- Source
- IEEE APCCAS 2000. 2000 IEEE Asia-Pacific Conference on Circuits and Systems. Electronic Communication Systems. (Cat. No.00EX394) Asia Pacific circuits and systems Circuits and Systems, 2000. IEEE APCCAS 2000. The 2000 IEEE Asia-Pacific Conference on. :686-689 2000
- Subject
- Components, Circuits, Devices and Systems
Communication, Networking and Broadcast Technologies
Engineered Materials, Dielectrics and Plasmas
Memory architecture
Image coding
Transform coding
Costs
Quantization
Circuits
Image storage
Color
Electronic mail
Digital signal processing
- Language
In this paper a baseline JPEG encoder soft intellectual property (IP) is proposed together with a memory efficient preprocessing architecture for scanner to solve the bandwidth problem between PC and scanner. This JPEG IP features quantization tables that are reconfigurable at run time and compile time. It is a modularized and fully pipelined design with friendly interface, which makes it easier to be integrated into various application systems. It is silicon proven to run up to 40 MHz at 3.3 V. With the optimized preprocessing unit feeding data smoothly into JPEG core, it is a low cost and competitive solution for a scanner to have a compression function embedded.