A WR1.5 frequency multiplier using CMOS accumulation mode varactor device
- Resource Type
- Conference
- Authors
- Choi, S. H.; Yi, C.; Kim, M.
- Source
- 2016 Progress in Electromagnetic Research Symposium (PIERS) Progress in Electromagnetic Research Symposium (PIERS). :4666-4669 Aug, 2016
- Subject
- Engineered Materials, Dielectrics and Plasmas
Fields, Waves and Electromagnetics
Geoscience
Photonics and Electrooptics
Power generation
Varactors
Power measurement
Semiconductor device measurement
Mixers
Radio frequency
Bolometers
- Language
A WR1.5 frequency multiplier circuit using standard CMOS 65nm technology is presented. Careful choice of device and its gate size leads to fair amount of output power compared to other expensive high performance semiconductor process. Accumulation-mode varactor device is chosen for its high non-linearity and gate size of the varactor is enlarged until self-resonance occur at fundamental frequency. Simple doubler circuit is designed using single-balanced topology. Two types of power measurements are performed to verify results. The maximum output power of −21.8dBm is obtained at 59 GHz which is comparable output power considering process cost.