A Ring-Oscillator Sub-Sampling PLL With Hybrid Loop Using Generator-Based Design Flow
- Resource Type
- Conference
- Authors
- Wang, Zhongkai; Choi, Minsoo; Wright, John; Lee, Kyoungtae; Liu, Zhaokai; Yin, Bozhi; Han, Jaeduk; Du, Sijun; Alon, Elad
- Source
- 2022 IEEE International Symposium on Circuits and Systems (ISCAS) Circuits and Systems (ISCAS), 2022 IEEE International Symposium on. :2881-2885 May, 2022
- Subject
- Components, Circuits, Devices and Systems
Power, Energy and Industry Applications
Robotics and Control Systems
Signal Processing and Analysis
Ring oscillators
Phase noise
Circuits and systems
Modulation
Manuals
Jitter
Hybrid power systems
PLL
sub-sampling
ring oscillator
hybrid
PLL generator
- Language
- ISSN
- 2158-1525
We present a ring-oscillator-based sub-sampling phase-locked loop (PLL) using a generator-based design flow. A hybrid loop with a delta-sigma ($\Delta \Sigma$) modulator is applied to reduce the loop filter (LF) area and the control ripple. The generator automatically produces the ring oscillator and PLL to meet the provided specifications. The 10-GHz PLL instance implemented in 28-nm planar process achieves RMS jitter of}299.5 fs and power of 9.9 mW from a 1-V supply.