Study on the Guard Rings for Latchup Prevention between HV-PMOS and LV-PMOS in a 0.15-µm BCD Process
- Resource Type
- Conference
- Authors
- Chen, Chao-Yang; Lee, Jian-Hsing; Nidhi, Karuna; Bin, Tzer-Yaa; Lin, Geeng-Lih; Ker, Ming-Dou
- Source
- 2021 IEEE International Reliability Physics Symposium (IRPS) Reliability Physics Symposium (IRPS), 2021 IEEE International. :1-4 Mar, 2021
- Subject
- Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Engineering Profession
Integrated circuits
Low voltage
Reliability engineering
Foundries
Integrated circuit reliability
Physics
Latchup
Guard Rings
Latchup Prevention
High-Voltage CMOS
bipolar-CMOS-DMOS (BCD) process
- Language
- ISSN
- 1938-1891
An abnormal lower latchup immunity is really induced by the guard rings which were originally applied to prevent latchup occurrence between the HV-PMOS and LV-PMOS in a 0.15-µm BCD process. The parasitic npn BJT, that exits between the guard rings from HV-NW (biased at highvoltage VDDH) to the LV-NW (biased at low-voltage VDDL), may cause a holding voltage lower than the voltage difference between VDDH and VDDL. To apply the guard rings for latchup prevention, the study results reported in this work are very important to the foundries and the IC design houses.