Design of Low Power Stacked Inverter Based SRAM Cell with Improved Write Ability
- Resource Type
- Conference
- Authors
- Chaudhary, D.; Muppalla, V.; Mukheerjee, A.
- Source
- 2020 IEEE Region 10 Symposium (TENSYMP) Region 10 Symposium (TENSYMP), 2020 IEEE. :925-928 Jun, 2020
- Subject
- Bioengineering
Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Computing and Processing
Engineered Materials, Dielectrics and Plasmas
Fields, Waves and Electromagnetics
General Topics for Engineers
Photonics and Electrooptics
Power, Energy and Industry Applications
Robotics and Control Systems
Signal Processing and Analysis
SRAM cells
Transistors
Power dissipation
Inverters
MOSFET
Leakage currents
Threshold current
power gating
leakage power
static power
static random access memory (SRAM)
- Language
- ISSN
- 2642-6102
This paper puts forth double ended low power static random access memory (SRAM) cell structure that uses low power stacked inverters to reduce the power dissipation. The power dissipation in static mode is further reduced by feeding the cross coupled inverters with lower supply voltage during hold mode along with power gating. Simulation results in the Cadence Virtuoso design environment using 65 nm technology library show a 47.8% saving in the total power dissipation, 20.14% saving in static power dissipation and 83% improvement in the energy delay product respectively, in contrast to the 6T regular SRAM cell. The stability analysis shows that the propounded SRAM cell has bigger write ability as opposed to the basic 6T SRAM cell using the N-curve methodology.