A 12 GHz heterodyne receiver for digital video broadcasting via satellite applications in silicon bipolar technology
- Resource Type
- Conference
- Authors
- Smerzi, S.A.; Copani, T.; Girlando, G.; Castorina, A.; Palmisano, G.
- Source
- 2004 IEEE MTT-S International Microwave Symposium Digest (IEEE Cat. No.04CH37535) Microwave symposium digest Microwave Symposium Digest, 2004 IEEE MTT-S International. 1:25-28 Vol.1 2004
- Subject
- Fields, Waves and Electromagnetics
Engineered Materials, Dielectrics and Plasmas
Fields, Waves and Electromagnetics
Aerospace
Communication, Networking and Broadcast Technologies
Photonics and Electrooptics
Digital video broadcasting
Satellite broadcasting
Silicon
Voltage-controlled oscillators
Integrated circuit synthesis
Synthesizers
Gain
Noise figure
Phase noise
Voltage
- Language
- ISSN
- 0149-645X
A single-chip 12 GHz silicon bipolar receiver for digital video broadcasting via satellite (DVB-S) applications is presented. The IC consists of a down-converter block and a PLL-based LO synthesizer. The receiver is based on a heterodyne architecture. For 12 GHz input signal it shows a con version gain of 38 dB, a single sideband noise figure of 7 dB and an output 1 dB compression point of +5 dBm. The VCO phase noise is -95 dBc/Hz at a 100 kHz offset from a 10.6 GHz carrier. The VCO tuning range is 2.2 GHz, extending from 8.6 GHz to 10.8 GHz. The current consumption of the integrated receiver is 160 mA with a 3.3 V voltage supply. This paper demonstrates the feasibility of a low-cost silicon bipolar technologies for a Ku-band DVB-S heterodyne receiver.