A Mixed-Signal Time-Domain Generative Adversarial Network Accelerator with Efficient Subthreshold Time Multiplier and Mixed-Signal On-Chip Training for Low Power Edge Devices
- Resource Type
- Conference
- Authors
- Chen, Zhengyu; Fu, Sihua; Cao, Qiankai; Gu, Jie
- Source
- 2020 IEEE Symposium on VLSI Circuits VLSI Circuits, 2020 IEEE Symposium. :1-2 Jun, 2020
- Subject
- Components, Circuits, Devices and Systems
Training
Gallium nitride
Time-domain analysis
Hardware
Generators
Adaptation models
Generative adversarial networks
- Language
- ISSN
- 2158-5636
This work presents a low-cost mixed-signal time-domain accelerator for generative adversarial network (GAN). A significant reduction in hardware cost was achieved through delicate architecture optimization for 8-bit GAN training on edge devices. An area efficient subthreshold time-domain multiplier was designed to eliminate excessive data conversion for mixed-signal computing enabling high throughput mixed-signal online training demonstrated in a 65nm CMOS test chip.