Processor Design in 3D Die-Stacking Technologies
- Resource Type
- Periodical
- Authors
- Loh, Gabriel H.; Xie, Yuan; Black, Bryan
- Source
- IEEE Micro Micro, IEEE. 27(3):31-48 Jun, 2007
- Subject
- Computing and Processing
Process design
Integrated circuit technology
Fabrication
Silicon
Integrated circuit interconnections
Wafer bonding
Microprocessors
Stacking
Topology
Chemical technology
processor architectures
computer systems organization
3D integration
- Language
- ISSN
- 0272-1732
1937-4143
Three-dimensional die-stacking integration stacks multiple layers of processed silicon with a very high-density, low-latency layer-to-layer interconnect. After presenting a brief background on 3D die-stacking technology, this article gives multiple case studies on different approaches for implementing single-core and multicore 3D processors and discusses how to design future microprocessors given this emerging technology.