A 1-Tb 4-b/cell 4-Plane 162-Layer 3-D Flash Memory With 2.4-Gb/s IO Interface
- Resource Type
- Periodical
- Authors
- Yuh, J.H.; Li, Y.J.; Li, H.; Oyama, Y.; Hsu, C.; Anantula, P.; Jeong, G.Y.S.; Amarnath, A.; Darne, S.; Bhatia, S.; Tang, T.; Arya, A.; Rastogi, N.; Ookuma, N.; Mizukoshi, H.; Yap, A.; Wang, D.; Kim, S.; Wu, Y.; Peng, M.; Lu, J.; Ip, T.; Malhotra, S.; Han, T.; Okumura, M.; Liu, J.; Sohn, J.J.; Chibvongodze, H.; Balaga, M.; Matsuda, A.; Chen, C.; K. V., I.; G., V.S.N.K.C.; Ramachandra, V.; Kato, Y.; Kumar, R.J.; Wang, H.; Moogat, F.; Yoon, I.; Kanda, K.; Shimizu, T.; Shibata, N.; Yanagidaira, K.; Kodama, T.; Fukuda, R.; Hirashima, Y.; Abe, M.
- Source
- IEEE Journal of Solid-State Circuits IEEE J. Solid-State Circuits Solid-State Circuits, IEEE Journal of. 58(1):316-328 Jan, 2023
- Subject
- Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Computing and Processing
Ash
Transistors
Decoding
Computer architecture
Throughput
Pins
Metals
3-D flash
BiCS flash
discrete Fourier transform (DFT)
IO design
NAND
peak power management (PPM)
program throughput
- Language
- ISSN
- 0018-9200
1558-173X
A 1 Tb 4-b/cell 162-layer 3-D flash memory achieves 15-Gb/mm2 areal density and delivers program throughput up to 60 MB/s and the best case tR of 65 $\mu \text{s}$ by employing 8-kB wordline (WL) central stair structure and contact-through-WL (CTW) architecture. IO speed of 2.4 Gb/s with low tapped termination/center tapped termination (LTT/CTT) combo driver is supported. This article also discusses data transfer energy reduction using VCCQ domain design and data bus inversion (DBI) technique. Novel time division peak power management (TD-PPM) feature can reduce system peak current while maximizing system performance. Cache and IO discrete Fourier transform (DFT) enable a high-speed testing at wafer level for test cost reduction.