A RISC-V-based FPGA Overlay to Simplify Embedded Accelerator Deployment
- Resource Type
- Conference
- Authors
- Bellocchi, Gianluca; Capotondi, Alessandro; Conti, Francesco; Marongiu, Andrea
- Source
- 2021 24th Euromicro Conference on Digital System Design (DSD) DSD Digital System Design (DSD) 2021 24th Euromicro Conference on. :9-17 Sep, 2021
- Subject
- Computing and Processing
Program processors
Digital systems
Tools
Cyber-physical systems
Software
Hardware
Energy efficiency
System level design
Overlay architecture
FPGA
Hardware accelerators
High level synthesis
HeSoC
- Language
Modern cyber-physical systems (CPS) are increasingly adopting heterogeneous systems-on-chip (HeSoCs) as a computing platform to satisfy the demands of their sophisticated workloads. FPGA-based HeSoCs can reach high performance and energy efficiency at the cost of increased design complexity. High-Level Synthesis (HLS) can ease IP design, but automated tools still lack the maturity to efficiently and easily tackle system-level integration of the many hardware and software blocks included in a modern CPS. We present an innovative hardware overlay offering plug-and-play integration of HLS-compiled or handcrafted acceleration IPs thanks to a customizable wrapper attached to the overlay interconnect and providing shared-memory communication to the overlay cores. The latter are based on the open RISC-V ISA and offer simplified software management of the acceleration IP. Deploying the proposed overlay on a Xilinx ZU9EG shows ≈ 20% LUT usage and ≈ 4× speedup compared to program execution on the ARM host core.