Ising machines, hardware accelerators based on the Ising model, have recently gained interest as alternative computers for solving combinatorial optimization problems (COPs) in various industrial fields with practical applications such as logistics, supply chain optimization, and financial portfolio management. One of the early implementations of the Ising machines is a quantum annealer [1] that is built with superconducting qubits operating at an extremely low operating temperature (15-20mK). The quantum machine implemented 2048 qubits that are connected in a Chimera graph topology with a degree of 6, which indicates the number of interactions per qubit, where eight qubits are connected in a local bipartite graph with two separate groups – i.e., a $4\times 4$ fully connected qubit structure with no connection between qubits in the same group of four qubits. CMOS-based ASIC Ising accelerators [2–5] have been developed to overcome the quantum annealer challenges: low operating temperature, high operation costs, and large errors. Prior works have introduced digital and mixed-signal Ising machines. While operating at room temperature using low-cost CMOS technologies, the existing ASIC Ising machines have their own limitations. The density of the implemented spins – the computing units of the ASIC Ising machines, which are similar to the qubits of quantum computers – have been restricted to ~1k spins per 1mm 2 ; while, their hardware topologies have been limited to simple graphs (such as lattice [4] or King’s graphs [2, 5]), restricting their applications to simpler problems due to their limited connectivity and reconfigurability. Moreover, traditional discrete-time digital-circuit operations, with limited parallelism due to the required sequential Ising operations, require more time to find a solution.