Currently in deep sub-micron technologies such as 16 nm and smaller, requirement of portable devices focus designers' attention on low power design of CMOS circuits and systems, using different low power techniques, trying to decrease dynamic and/or leakage power. One of the widely employed power optimization methods is multi voltage design, used to reduce power by dividing IC into voltage IC domains. This paper presents a new approach of multi voltage design technique, generalizing it, to use “n” voltage domains with “n” different supply voltages, providing efficient power reduction of digital systems such as processor. Basically, voltage areas match sub modules of processor with addition of modified version of adaptive voltage scaling.