The SELENE Deep Learning Acceleration Framework for Safety-related Applications
- Resource Type
- Conference
- Authors
- Medina, L.; Carrion, S.; Andreu, P.; Picornell, T.; Flich, J.; Hernandez, C.; Sandoval, M.; Sainz, M.; Lefebvre, C.-A.; Ronnback, M.; Matschnig, M.; Wess, M.; Taucher, H.
- Source
- 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE) Design, Automation & Test in Europe Conference & Exhibition (DATE), 2022. :636-639 Mar, 2022
- Subject
- Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Computing and Processing
Robotics and Control Systems
Deep learning
Costs
Multicore processing
Neural networks
Real-time systems
Hardware
System-on-chip
Neural Networks
real-time
Autonomy
- Language
- ISSN
- 1558-1101
The goal of the H2020 SELENE project is the development of a flexible computing platform for autonomous applications that includes built-in hardware support for safety. The SELENE computing platform is an open-source RISC-V heterogeneous multicore system-on-chip (SoC) that includes 6 NOEL-V RISC-V cores and artificial intelligence accelerators. In this paper, we describe the approach followed in the SELENE project to accelerate neural network inference processes. Our intermediate results show that both the FPGA and ASIC accel-erators provide real-time inference performance for the analyzed network models at a reasonable implementation cost.