Demonstration of speed enhancements on an industrial circuit through application of non-zero clock skew scheduling
- Resource Type
- Conference
- Authors
- Velenis, D.; Tang, K.T.; Kourtev, I.S.; Adler, V.; Baez, F.; Friedman, E.G.
- Source
- ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Electronics, circuits and systems Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on. 2:1021-1025 vol.2 2001
- Subject
- Components, Circuits, Devices and Systems
Clocks
Job shop scheduling
Processor scheduling
Timing
Circuit optimization
Software tools
Scheduling algorithm
Signal generators
Delay
Software libraries
- Language
A demonstration of the application of non-zero clock skew scheduling to enhance the speed characteristics of several functional unit blocks in a high performance processor is presented. It is shown that non-zero clock skew scheduling can improve circuit performance while relaxing the strict timing constraints of the critical data paths within a high speed system. A software tool implementing a non-zero clock skew scheduling algorithm is described together with a methodology that generates the required clock signal delays by replacing clock buffers from predesigned cell libraries. Timing margin improvements of up to 18% are achieved through the application of non-zero clock skew scheduling in certain functional blocks of an industrial high performance microprocessor.