Demonstration of power enhancements on an industrial circuit through delay management of non-critical data paths
- Resource Type
- Conference
- Authors
- Velenis, D.; Tang, T.K.; Kourtev, I.S.; Adler, V.; Baez, F.; Friedman, E.G.
- Source
- Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No.01TH8558) ASIC/SOC conference ASIC/SOC Conference, 2001. Proceedings. 14th Annual IEEE International. :30-33 2001
- Subject
- Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Delay
Energy management
Power dissipation
Clocks
Power supplies
Circuit simulation
System-on-a-chip
Voltage
Capacitance
Engineering management
- Language
On-chip power dissipation has become a fundamental design issue in high performance integrated circuits. A technique to significantly reduce the power dissipated in the non-critical data paths of an industrial circuit is demonstrated. The application of this technique with non-zero clock skew scheduling to the slower data paths is also described. Simulation results demonstrating the application of this technique to certain functional blocks of a high performance microprocessor are presented. A greater than 80% power savings is achieved in specific circuit blocks.