A 14-GHz Bang-Bang Digital PLL with sub-150fs Integrated Jitter for Wireline Applications in 7nm FinFET
- Resource Type
- Conference
- Source
- 2019 IEEE Custom Integrated Circuits Conference (CICC) Custom Integrated Circuits Conference (CICC), 2019 IEEE. :1-4 Apr, 2019
- Subject
Components, Circuits, Devices and Systems Engineering Profession Phase locked loops Jitter Varactors Clocks Phase noise Tuning Bang-Bang PLL limit cycle jitter class-C DCO inversion mode varactor look-ahead filter transceiver clock generation PAM-4 calibrated current source - Language
- ISSN
- 2152-3630