设计了采样频率为640MHz、过采样率为64的高频数字抽取滤波器.该数字抽取滤波器由CIC(Cascaded Integrator Comb)滤波器(降16倍)、CIC补偿滤波器(降2倍)和半带滤波器(降2倍)组成.为了实现高频工作,CIC滤波器采用两级结构,第一级采用多相分解技术,使大部分结构工作在较低时钟频率下,极大地降低了CIC的功耗,第二级采用传统结构.CIC补偿滤波器使信号通带平坦,半带滤波器满足了阻带的衰减要求.为了验证数字滤波器的性能,搭建了四阶前馈—反馈结构∑△调制器,作为数字抽取滤波器的输入,最终在输入信号频率为0.5 MHz时,数字抽取滤波器输出的信噪比为97.40 dB.
The paper designs a high-frequency digital decimation filter with a sample rate as high as 640 MHz and a decimation factor of ‘64’.This digital decimation filter consists of CIC filter,CIC compensator filter and half-band filter.The CIC filter uses structure of two stages for operating in high frequency.The first stage adopts polyphase decomposition to decrease the operating frequency so that the power consumption can be reduced significantly,and the second stage uses traditional structure.The CIC compensation part achieves a fiat passband and the half-band filter meets the demand of stopband attenuation.In order to verify the performance of digital decimation filter,the paper designs a four stage feed forward-feedback ∑△modulator as the input of digital decimation filter.Under an input signal frequency of 0.5 MHz,SNR is 97.40 dB at last.