A 4.6 GHz 162 Mb SRAM Design in 22 nm Tri-Gate CMOS Technology With Integrated Read and Write Assist Circuitry
- Resource Type
- Authors
- Kaizad Mistry; Zheng Guo; John Keane; Mesut Meterelliyoz; Kevin Zhang; Yih Wang; M. Bohr; Uddalak Bhattacharya; Fatih Hamzaoglu; Eric Karl; Yong-Gee Ng
- Source
- IEEE Journal of Solid-State Circuits. 48:150-158
- Subject
- Engineering
Hardware_MEMORYSTRUCTURES
business.industry
Transistor
Electrical engineering
Hardware_PERFORMANCEANDRELIABILITY
Transient voltage suppressor
law.invention
Integrated injection logic
CMOS
law
Low-power electronics
Hardware_INTEGRATEDCIRCUITS
Static random-access memory
Electrical and Electronic Engineering
business
Electronic circuit
Voltage
- Language
- ISSN
- 1558-173X
0018-9200
A 162 Mb voltage-scalable SRAM array design in 22 nm CMOS tri-gate logic technology is presented. The designs of a 0.092 μm2 bitcell for high density applications and a 0.108 μm2 bitcell for improved performance at low supply voltage are introduced. Transient voltage collapse and wordline under-drive peripheral assist circuits improve low-voltage operating margins and address fin quantization. Co-optimization of tri-gate transistors and circuits allow up to 70% improvement in frequency at low voltages and 85% improvement in density from a scaled 32 nm design. The low-voltage array design demonstrates 4.6 GHz operation at 1.0 V and 3.4 GHz operation at 0.8 V while achieving array densities up to 6.7 Mb/mm2.