This paper will present the recent work done at CEA-LITEN for the development of Printed Transistor circuits. In particular, through Collaborative Project and internal Development, CEA-LITEN and partners have been working on the transfer and scale-up of OTFT Circuits from Lab to Printing Pilot Line (GEN1). The paper will discuss the challenges and requirements for the materials at the different technological level from process to device as well as for circuits design and integration into hybrid system. The material strategy and inks developed for robust printing capability and the engraving technologies engineered for the downscaling of printed pattern down to 150 µm and beyond will be introduced. Electrical performances and electrical bias stress stability of the OTFT fabricated on GEN1 pilot line will be presented and discussed (µFE > 2cm²/V/s; Vt~ -3..-4.5 V). Finally, in the last section the paper will present the current capability of technology for smart sensor applications and discuss the current limitation and track of improvement through innovative materials. Figure 1