Analog Multiplying/Weighting VLSI Cells for SVM Classifiers
- Resource Type
- Authors
- Mihaela Cirlugea; Robert Groza; Lelia Festila; Lorant Andras Szolga
- Source
- Lecture Notes in Computer Science ISBN: 9783540855668
KES (3)
- Subject
- Very-large-scale integration
Support vector machine
Mathematical optimization
Computer science
Simple (abstract algebra)
Algorithm
Weighting
Domain (software engineering)
- Language
VLSI support vector machine classifiers require a large amount of calculations, therefore their implementation needs high density, high speed and low power circuits. In a SVM architecture based on a multiplying law the main building blocks are multipliers. We propose in this paper multiplying and weighting cells, developed by using a model consisting of a compound of two inverse non-linear functions. This procedure is suitable for VLSI implementation because it permits the use of simple nonlinearized standard DA cells that compensate each other nonlinearities to obtain an extended domain of operation. The resulted weighting/multiplying cells were analyzed and tested by simulations.