A processor core for 32 kbit/s G.726 ADPCM codecs
- Resource Type
- Authors
- J. Vehvilainen; Jari Nurmi
- Source
- ISCAS
- Subject
- Multi-core processor
Adaptive differential pulse-code modulation
business.industry
Computer science
Cycles per instruction
Integrated circuit design
computer.file_format
Instruction set
Logic synthesis
Application-specific integrated circuit
Computer architecture
VHDL
Codec
business
Harvard architecture
computer
Digital signal processing
Computer hardware
computer.programming_language
- Language
This paper describes an application specific DSP core designed to be used in a CCITT 32 kbit/s G.726 Adaptive Differential Pulse Code Modulation (ADPCM) codec. The instruction set architecture and the programming model of the DSP core were derived from an algorithm profile and complexity analysis and the core was implemented using VHDL and logic synthesis. Architecture design efforts were concentrated on finding the minimum amount of hardware resources which could implement the required functionality within the clock cycle count limit. The result is a Harvard architecture processor core which can be used to implement the 32 kbit/s G.726 ADPCM encoding/decoding functions with very modest external instruction and data memory requirements. In a typical configuration the processor can perform a full encode/decode operation for one sample in less than 1100 clock cycles. A gate-level implementation of less than 4000 gates of silicon area was created using logic synthesis for a standard cell technology.