Performance and layout effects of SiGe channel in 14nm UTBB FDSOI: SiGe-first vs. SiGe-last integration
- Resource Type
- Authors
- Pierre Perreau; Michel Haond; Didier Dutartre; R Berthelon; Alain Claverie; A. Pofelski; Emmanuel Josse; Francois Andrieu; E. Baylac
- Source
- Solid-State Device Research Conference (ESSDERC), 2016 46th European
Solid-State Device Research Conference (ESSDERC), 2016 46th European, 2016, Unknown, Unknown Region. pp.127-130, ⟨10.1109/ESSDERC.2016.7599604⟩
2016 46th European Solid-State Device Research Conference (ESSDERC)
ESSDERC
- Subject
- Materials science
SiGe
Electrical model
Gate length
Integration
layout effects
02 engineering and technology
Ring oscillator
Epitaxy
01 natural sciences
Strain
Stress (mechanics)
chemistry.chemical_compound
0103 physical sciences
Electronic engineering
Layout dependences
Electrical modeling
Silicon alloys
010302 applied physics
[PHYS]Physics [physics]
Solid state devices
business.industry
Germanium
Delay reduction
021001 nanoscience & nanotechnology
Integration scheme
Reconfigurable hardware
FDSOI
Silicon-germanium
chemistry
Logic gate
Optoelectronics
0210 nano-technology
business
Communication channel
- Language
- English
cited By 0; International audience; We report on the layout effects in strained SiGe channel FDSOI pMOSFETS down to 20nm gate length. Two SiGe integration schemes are compared: the SiGe-first approach, with Ge-enrichment performed prior to the STI module and the SiGe-last approach using only a SiGe epitaxy after the STI module. We evidence reduced layout effects in the SiGe-last integration featuring Si/SiGe bilayer. SiGe-last shows -39% mobility for 170nm narrow 2μm long channel, but +21% Ieff at Lg=20nm and gate-to-STI distance of 59nm. It is translated into a -15% delay reduction for ring oscillators of 1-finger inverters. Layout dependences are explained by physical strain measurements and reproduced by a stress-based electrical model. © 2016 IEEE.