Frame, or kerf or scribe line, is an area in reticle surrounding individual chip/die. It is used to place various marks for process control purposes, such as lithography alignment and overlay marks. With the increasing complexity of semiconductor processes, more factors need to be considered and mistakes can be made, especially when multi-projects devices are combined into one reticle at early R&D phase. We have developed a methodology to help to design frame marks which is error-proofing and robust to various process tuning including material changes. This includes placement guide and thorough simulations predictions. This has led to satisfactory results.