Study on the Key Influencing Factors of Single-Event-Upset Sensitivity in 65nm CMOS Sequencing Logic Circuit
- Resource Type
- Conference
- Authors
- Sai, LI; Rui, CHEN; Jianwei, HAN; YingQi, MA; ShiPeng, SHANGGUAN; Xiang, ZHU; Yue, LI
- Source
- 2018 International Conference on Radiation Effects of Electronic Devices (ICREED) Radiation Effects of Electronic Devices (ICREED), 2018 International Conference on. :1-5 May, 2018
- Subject
- Aerospace
Components, Circuits, Devices and Systems
Nuclear Engineering
Single event upsets (SEUs)
operating pattern
clock frequency
supply voltage
circuit structure
- Language
Single-event-upset (SEU) sensitivity of sequencing logic circuits (D flip-flops) fabricated in 65-nm bulk CMOS process is investigated as a function of operating pattern, clock frequency, supply voltage and circuit structure by using pulsed laser.