Wafer Level Chip Scale Package copper pillar probing
- Resource Type
- Conference
- Authors
- Chen, Hao; Lin, Hung-Chih; Peng, Ching-Nen; Wang, Min-Jer
- Source
- 2014 International Test Conference Test Conference (ITC), 2014 IEEE International. :1-6 Oct, 2014
- Subject
- Computing and Processing
Probes
Micromechanical devices
Resistance
Copper
Oxidation
Silicon
Optimization
Integration fan-out wafer level chip scale package (InFO WLCSP)
copper pillar
known-good-die (KGD)
wafer level final test (WLFT)
redistribution layer (RDL)
probe card
MEMS (micro electro mechanical system)
automatic test equipment (ATE)
touch-down
polish
overdrive
- Language
- ISSN
- 1089-3539
2378-2250
This paper introduces a probing methodology for Integrated Fan Out Wafer Level Chip Scale Packaging (InFO WLCSP) which has the promise of being a very cost effective solution to achieve “More than Moore's law” for mobile devices - more so than 3D integrated circuits (3DIC). InFO WLCSP can use either Aluminum (Al) pads or Copper (Cu) pillars as contact interfaces. Cu pillars without solder caps are selected as the contact interface due to their superior area and cost efficiency. However, there are some challenges due to Cu oxidation and its small size. In this paper we propose a novel methodology that leads to a very high precision test resulting in better yield for mass production of InFO WLCSP packages. We will show results on some industrial designs to validate our claims.