Disclosed is a circuit and method for reducing control code transmission between a line card and a switching fabric. One embodiment includes a memory receiving (and storing) data transmitted at a second rate during a first period of time. A quantity of data in the memory at time t, q(t), is compared with first, second, third, and fourth quantity values. The memory may receive data transmitted at the first rate if q(t) is less than the second, third and fourth values but greater than the first value. The memory may receive data transmitted at the third rate if q(t) is greater than the first, second, and third values but less than the fourth value. The memory may receive data transmitted at the second rate if q(t) is greater than the first and second values but less than the third and fourth values.