Investigation of shape etching on multi-layer SiO2/poly-Si for 3D NAND architecture
- Resource Type
- Conference
- Authors
- Yang, Zusing; Hsu, Fang-Hao; Lin, Lo Yueh; Lee, Hong-Ji; Lian, Nan-Tzu; Yang, Tahone; Chen, Kuang-Chao; Lu, Chih-Yuan
- Source
- ASMC 2013 SEMI Advanced Semiconductor Manufacturing Conference Advanced Semiconductor Manufacturing Conference (ASMC), 2013 24th Annual SEMI. :24-26 May, 2013
- Subject
- Components, Circuits, Devices and Systems
Power, Energy and Industry Applications
Flash memories
Etching
Three-dimensional displays
Shape
Films
Loading
Very large scale integration
3D NAND
3DVG NAND
bit line
multi-layer SiO2/Poly-Si
plasma etch
- Language
- ISSN
- 1078-8743
2376-6697
This paper describes a simple and systematic etching approach for the preparation of smooth vertical bit line (BL), stacked with multiple layers of SiO 2 (OX) and poly-Si (PL) films for the use in three-dimensional vertical gate (3DVG) NAND flash application. A successful shape evolution from tapered to acceptable BL profile with sub-10 nm critical dimension (CD) difference between bottom and top PL layers is performed by a recipe consisting of etch-trim-etch processing steps. This novel etch sequence is more advantageous than that of traditional simultaneous etch-deposition process for controlling profile shape of the multi-layer stack in the 3D NAND flash manufacturing.