An effective methodology of predicting the intrinsic failure rates 10 8 samples at the transistor level was stressed at the same time, and its distribution was measured for the first time. Failure rates estimated to chip level with this data was consistent with those measured at the chip level, and is also applicable to devices which follows weibull clustering distribution. With this wafer main-chip characterization capable of applying high acceleration voltages, the 12nm DDR5 DRAM demonstrated the gate oxide reliability 10 4 at the package level. In addition, all reliability including FEOL/MEOL/BEOL were also characterized using test structures and wafer main-chips.