Maximum delay variation temperature-aware standard cell design
- Resource Type
- Conference
- Authors
- Pons, Marc; Nagel, Jean-Luc; Piguet, Christian
- Source
- 2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012) Electronics, Circuits and Systems (ICECS), 2012 19th IEEE International Conference on. :296-299 Dec, 2012
- Subject
- Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Fields, Waves and Electromagnetics
Delay
Libraries
Temperature sensors
Standards
Temperature measurement
Equations
Sensitivity
- Language
Standard cell design suffers from temperature-induced delay uncertainty. In this paper we propose two methodologies to cope with this issue before the logic synthesis step without modifying the standard flow. Both methodologies are based on the study of the cell maximum delay sensitivity to temperature variations to select the cells of the library to be used for the synthesis. We provide icyflex2 CSEM processor synthesis to demonstrate the delay variability reduction obtained.