Integration of multi-level copper metallization into a high performance sub-0.25 /spl mu/m CMOS technology
- Resource Type
- Conference
- Authors
- Venkatesan, S.; Venkatraman, R.; Jain, A.; Mendonca, J.; Anderson, S.; Angyal, M.; Capasso, C.; Cope, J.; Crabtree, P.; Das, S.; Farkas, J.; Filipiak, S.; Fiordalice, B.; Hamilton, G.; Herrick, M.; Kawasaki, H.; Islam, R.; King, C.; Klein, J.; Lii, T.; Misra, V.; Reid, K.; Simpson, C.; Smith, B.; Sparks, T.; Watts, D.; Weitzman, E.J.; Wilson, B.
- Source
- Proceedings of the 1998 Second IEEE International Caracas Conference on Devices, Circuits and Systems. ICCDCS 98. On the 70th Anniversary of the MOSFET and 50th of the BJT. (Cat. No.98TH8350) Devices, circuits and systems Devices, Circuits and Systems, 1998. Proceedings of the 1998 Second IEEE International Caracas Conference on. :146-152 1998
- Subject
- Components, Circuits, Devices and Systems
Copper
Metallization
CMOS technology
Delay
MOS devices
Isolation technology
Temperature
Hot carriers
Thermal stresses
Conductivity
- Language
A high performance sub-0.25 /spl mu/m CMOS technology has been developed with six levels of planarized copper interconnects. 0.15 /spl mu/m transistors (L/sub gate/=0.15 /spl mu/m) are optimized for 1.8 V operation to provide high performance with low power-delay products and excellent reliability. Copper has been integrated into the back-end to provide low resistance interconnects to minimize wiring induced RC delays.