A pipelined SAR ADC with loading-separating technique in 90-nm CMOS technology
- Resource Type
- Conference
- Authors
- Lin, Sheng-Hsiung; Lin, Jin-Fu; Huang, Guan-Ying; Chang, Soon-Jyh
- Source
- 2012 IEEE Asia Pacific Conference on Circuits and Systems Circuits and Systems (APCCAS), 2012 IEEE Asia Pacific Conference on. :264-267 Dec, 2012
- Subject
- Components, Circuits, Devices and Systems
Communication, Networking and Broadcast Technologies
Computing and Processing
Signal Processing and Analysis
Switches
Capacitors
Arrays
Timing
CMOS integrated circuits
Loading
Bandwidth
- Language
This paper presents a 12-bit 50-MS/s pipelined SAR analog-to-digital converter (ADC) with loading-separating technique. The proposed loading-separating technique relaxes output loading of multiplying digital-to-analog converter (MDAC) and increases the time budget of bit cycling for the 2 nd stage. In addition, a split-path amplification MDAC is proposed to enhance amplifier's gain and bandwidth. The ADC core occupies an active area of 0.27 mm 2 in TSMC 90-nm 1P9M CMOS process. The measured results show that the proposed ADC achieves 63.56 dB SNDR with 2.17 mW power consumption.