MARSv2: Multicore and Programmable Reconstruction Architecture SRAM CIM-Based Accelerator with Lightweight Network
- Resource Type
- Conference
- Authors
- Hsieh, Chia-Yu; Lin, Shih-Ting; Li, Zhaofang; Lu, Chih-Cheng; Chang, Meng-Fan; Tang, Kea-Tiong
- Source
- 2022 IEEE 4th International Conference on Artificial Intelligence Circuits and Systems (AICAS) Artificial Intelligence Circuits and Systems (AICAS), 2022 IEEE 4th International Conference on. :383-386 Jun, 2022
- Subject
- Components, Circuits, Devices and Systems
Performance evaluation
Multicore processing
Convolution
Circuits and systems
Pipelines
Random access memory
Computer architecture
computing-in-memory
deep learning
sparsity
CNN accelerator
- Language
Computing-in-memory (CIM) systems reduce the degree of large-scale data movement by performing computation on the memory; this avoids a von Neumann bottleneck. Because of its low-power characteristic, CIM has demonstrated great potential for increasing the energy efficiency of edge devices. This paper presents a multicore and programmable reconstruction architecture using static random-access memory (SRAM) CIM-based accelerator with lightweight network. The proposed architecture uses SRAM CIM macro as the processing element, supporting sparse convolutional neural network computing. This architecture achieves 15.16 TOPS/W system energy efficiency and 747.6 GOPS on the CIFAR10 data set.