SRAM VMIN yield challenge in 40nm embedded NVM process
- Resource Type
- Conference
- Authors
- Luo, L. Q.; Wang, D. X.; Zhang, F.; Tan, J. B.; Chow, Y. T.; Kong, Y. J.; Huang, J. Y.; Liu, Y. M.; Oh, M.; Balan, H.; Khoo, P.; Chen, C. Q.; Liu, B. H.; Shum, D.; Shubhakar, K.; Pey, K. L.
- Source
- 2015 IEEE 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits Physical and Failure Analysis of Integrated Circuits (IPFA), 2015 IEEE 22nd International Symposium on the. :115-118 Jun, 2015
- Subject
- Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Engineering Profession
Photonics and Electrooptics
Random access memory
Nonvolatile memory
Implants
Grain size
Standards
Degradation
Logic gates
- Language
- ISSN
- 1946-1542
1946-1550
Embedded non-volatile memory (NVM) introduces additional thermal processes to a logic process flow and the impact from this extra thermal budget becomes more considerable with continued device scaling. This paper investigates the mechanism of SRAM V MIN degradation in a 40nm embedded NVM process and provides a solution to address the degradation caused. Failure analysis shows enlarged poly grain size for SRAM PMOS due to the NVM thermal processes, resulting in a large shift in threshold voltage. The results show that introduction of a p-poly boron pre-dope greatly helps to recover the SRAM V MIN . The mechanism for the V MIN recovery is also explained, with further high-temperature SRAM V MIN studies showing the effectiveness of p-poly pre-dope even at elevated temperatures.