A low drift programmable video clock synthesiser
- Resource Type
- Conference
- Authors
- Lahuec, C.; Horan, J.; Duigan, J.
- Source
- 11th IEEE Mediterranean Electrotechnical Conference (IEEE Cat. No.02CH37379) MELECON 2002 Electrotechnical Conference, 2002. MELECON 2002. 11th Mediterranean. :121-125 2002
- Subject
- Bioengineering
Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Computing and Processing
Engineered Materials, Dielectrics and Plasmas
Engineering Profession
Fields, Waves and Electromagnetics
General Topics for Engineers
Clocks
Phase noise
Phase locked loops
Ring oscillators
Delay lines
Jitter
Noise generators
Topology
CMOS process
Testing
- Language
This paper presents a video clock synthesiser. The block is programmable, it accepts input frequencies from 20 kHz to 5 MHz and produces output frequencies up to 200 MHz. The rms jitter is 20 ps and the phase drift is less than 0.5 ns which represents an improvement by a factor of 6 on Begueret et al. (2001). The device VDD sensitivity is 0.18%/V, this makes it suitable for integration in noisy ASICs. The area is 1.2 mm/sup 2/ in 0.25 /spl mu/m CMOS and it consumes 17 mW at 110 MHz.