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1 .
Exploring the Limits of Cobalt Liner Thickness in Advanced Copper Interconnects
저자
by
Kangguo Cheng
;
J. Maniscalco
;
O. van der Straten
;
Huai Huang
;
Kisik Choi
, et al.
소스
IEEE Electron Device Letters
. 40:1804-1807
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7 .
EM performance improvements for Cu interconnects with Ru-based liner and Co cap in advanced nodes : (Invited)
저자
by
Motoyama Koichi
.
소스
2021 IEEE International Interconnect Technology Conference (IITC)
.
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3 .
Co-doped Ru liners for highly reliable Cu interconnects with selective Co cap
저자
by
O. van der Straten
;
Scott DeVries
;
H. Seo
;
Motoyama Koichi
;
J. Maniscalco
, et al.
소스
2020 IEEE International Interconnect Technology Conference (IITC)
.
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7 .
CMP Development for Ru Liner Structures beyond 14nm
저자
by
Donald F. Canaperi
;
B. Peethala
;
Motoyama Koichi
;
Raghuveer R. Patlolla
;
Theodorus E. Standaert
, et al.
소스
ECS Journal of Solid State Science and Technology
. 7:P397-P401
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7 .
Experimental Study of PVD Cu/CVD Co Bilayer Dissolution for BEOL Cu Interconnect Applications
저자
by
Xunyuan Zhang
;
B. Peethala
;
Takeshi Nogami
;
James J. Demarest
;
O. van der Straten
, et al.
소스
ECS Transactions
. 80:297-309
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7 .
Mechanisms of Electromigration Damage in Cu Interconnects
저자
by
Lynne Gignac
;
Hosadurga Shobha
;
Paul S. McLaughlin
;
M. Ali
;
Chao-Kun Hu
, et al.
소스
2018 IEEE International Electron Devices Meeting (IEDM)
.
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7 .
Via resistance and reliability trends in copper interconnects with ultra-scaled barrier layers
저자
by
Huai Huang
;
Nicholas A. Lanzillo
;
Motoyama Koichi
;
Terry A. Spooner
;
Robert R. Robison
.
소스
Applied Physics Letters
. 116:164103
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7 .
Ru Liner Scaling with ALD TaN Barrier Process for Low Resistance 7 nm Cu Interconnects and Beyond
저자
by
Yb. Kim
;
Huai Huang
;
Theodorus E. Standaert
;
Chao-Kun Hu
;
Motoyama Koichi
, et al.
소스
2018 IEEE International Interconnect Technology Conference (IITC)
.
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7 .
Modified ALD TaN Barrier with Ru Liner and Dynamic Cu Reflow for 36nm Pitch Interconnect Integration
저자
by
B. Sheu
;
Prasad Bhosale
;
Roey Shaviv
;
P. McLaughlin
;
Takeshi Nogami
, et al.
소스
2018 IEEE International Interconnect Technology Conference (IITC)
.
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7 .
Impact of Line and Via Resistance on Device Performance at the 5nm Gate All Around Node and Beyond
저자
by
Terence B. Hook
;
Larry Clevenger
;
Nicholas A. Lanzillo
;
Motoyama Koichi
.
소스
2018 IEEE International Interconnect Technology Conference (IITC)
.
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