For high speed single-end parallel link system, its data rate is limited to simultaneous switching noise (SSN) by interface circuits. To reduce SSN, this paper proposes an orderly-drive parallel interface circuit. The parallel interface circuit transmits data at different phases of data period instead of simultaneously transmit data at the same phase. The current spike at power supply is averaged to all the data period thereby highly reducing SSN. To verify the proposed SSN suppression scheme, a single-ended driver and an 8-channels parallel link system are realized in TSMC 90nm CMOS technology. As compare to conventional parallel link system, the proposed design reveals a 75% of average SSN reduction and at all different data rates.