A voltage scaling model for performance evaluation in digital CMOS circuits
- Resource Type
- Conference
- Authors
- von Arnim, Klaus; Schruefer, Klaus; Baumann, Thomas; Hofmann, Karl; Schulz, Thomas; Pacha, Christian; Berthold, Joerg
- Source
- 2009 IEEE International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2009 IEEE International. :1-4 Dec, 2009
- Subject
- Components, Circuits, Devices and Systems
Robotics and Control Systems
Engineered Materials, Dielectrics and Plasmas
Photonics and Electrooptics
Semiconductor device modeling
CMOS digital integrated circuits
CMOS technology
Delay
Threshold voltage
Digital circuits
Dynamic voltage scaling
Temperature sensors
Temperature distribution
Software libraries
- Language
- ISSN
- 0163-1918
2156-017X
We present an easy to use method to extrapolate digital circuit performance and power from nominal to worst-case operating conditions. It allows the circuit designer to explore the design space over a continuous rage of voltages and temperatures and for different process conditions. Voltage scaling is identified as a key challenge for the 22nm technology node.